A semiconductor storage device in which a cell array is constituted by a plurality of dynamic memory cells each requiring refresh in order for data to be retained and which functions as a static random-access memory (SRAM (such a storage device is also referred to as “pseudo SRAM”) has been used. A Mobile Specified RAM Family [also referred to as an “MSRAM” (registered trademark)] also has been developed [see NEC Memory Product Information “Mobile Specified RAM” (search conducted on Dec. 7, 2003), Internet URL:
<http://www.necel.com/memory/japanese/products/msram/info.html>]. An MSRAM (registered trademark) is functionally compatible with a low-power-consumption SRAM and achieves a large increase in capacity (e.g., 16 to 128 M), which is not possible with an SRAM, by employing a DRAM memory cell.
In a semiconductor storage device such as an MSRAM (registered trademark), partial refresh, etc., is performed when the device is in the standby mode. If refresh is being executed at the time of a transition from the standby mode (when a chip-select signal /CS is at the high level) to the active mode, there is a possibility that the refresh operation will conflict with read/write access of the semiconductor storage device from the outside. For this reason, it is so arranged that the read/write activating operation in the cell array is performed after refresh ends following a delay of a prescribed delay time td (which is equivalent to the time for refresh to end) from the timing of the transition from the inactive to the active state of the chip-select signal /CS, as illustrated in FIG. 6A. In FIG. 6A, “Word” indicates the interval of activation of a selected word line, “Refresh” represents a word line corresponding to a refresh address, and R/W indicates a high-potential interval (pulse voltage waveform) of the word line corresponding to access address of read/write.
Further, since there is the possibility of a conflict with internal refresh at the time of address selection, it is so arranged that the read/write activating operation is performed following a delay of a prescribed delay time td from the timing of the address-signal transition (finalization of the address signal), as indicated in FIG. 6B.
On the other hand, with a general-purpose DRAM product, it is required that refresh be performed externally periodically based upon the data retention characteristic (cell leak characteristic) even in an active interval in which refresh is not being carried out. That is, it is necessary to interrupt the active interval and perform refresh. In this case, throughput of the memory declines owing to insertion of refresh.
Furthermore, in a semiconductor storage device of SRAM specifications using a DRAM cell, an arrangement in which a WAIT pin is provided to halt external access at the time of internal-refresh execution is known [MICRON 4 MEG×16, 2 MEG×16 ASYNC/PAGE/Burst CellularRAM MEMORY, pp. 5, 10, (search conducted on Nov. 12, 2003), Internet URL: <http://download.micron.com/pdf/products/psram/burst_cellularram.pdf>]. FIG. 8 illustrates an example of the structure of such a semiconductor storage device. A CellularRAM (TM) shown in FIG. 8 has a self-refresh function. Hidden refresh requires no support of refresh from an external system controller (not shown) and has no influence upon read/write performance. In FIG. 8, a refresh configuration register 203 sets how refresh of a DRAM array 201 is performed. In order to reduce standby current, the device has mechanisms for partial refresh, which refreshes only the part that contains essential data, for temperature-compensated refresh, which controls the refresh rate based upon the device operating temperature, and for deep power-down, which halts the refresh operation. In FIG. 8, CLK represents a synchronizing clock signal, ADV# a control signal indicating that a valid address exists on the address bus, and CRE a configuration-register enable signal. When CRE is high, writing is performed to the refresh configuration register 203 and to a bus configuration register 204. CE# is a chip-enable signal. When this signal is in the high level, the device transitions to standby. OE# represents an output-enable signal, WE# a write-enable signal, LB# a low byte-enable signal and UB# a high byte-enable signal. DQ is a data input/output terminal. WAIT is used to arbitrate conflict between refresh and the read/write operation. This arrangement is such that when a refresh trigger is generated from a refresh timer (not shown), the WAIT signal is activated (sent to the low level) to notify the external system memory controller (not shown) and delay read/write access.
[Non-Patent Document 1]
NEC Memory Product Information “Mobile Specified RAM” (search conducted on Dec. 7, 2003), Internet URL: http://www.necel.com/memory/japanese/products/msram/info.html
[Non-Patent Document 2]
MICRON 4 MEG×16, 2MEG×16 ASYNC/PAGE/Burst CellularRAM MEMORY, pp. 5, 10, (search conducted on Nov. 12, 2003), Internet URL: http://download.micron.com/pdf/products/psram/burst_cellularram.pdfl